#define CREG_BASE   0xbfd00000
#define CLOCK_CTRL0 0x220
#define CLOCK_CTRL2 0x228
#define CHIP_SAMPLE0 0x210

#define CPUPLL_LDF_OFFSET   1
#define CPUPLL_ODF_OFFSET   8

//Fout = Fin * ldf / 2^odf
//set user CPUPLL configure directly, make sure the defined value NOT exceed the min and max
//CPUPLL_LDF    //7 ~ 127
//CPUPLL_ODF    //0 ~ 7

	//enable dvfs in acpi to setup default freq div
	li  v0, 0xbfef0000
	lw  v1, (v0)
	or  v1, 0x3a00
	xor v1, 0x200
	sw  v1, (v0)
	li  v1, (3<<15)|(1<<9)|(1<<1)
	sw  v1, 0x3c(v0)

	//sysclk = 25Mhz * 120 = 3000Mhz
sbc_pll_cfg:
	li    t0, CREG_BASE
// [12]sel, [11]pd, [10:8]odf, [7:1]ldf, [0]set
// 25MHz            0      40*3(0x78)  0
	li    t1, 0x8f0
	sw    t1, CLOCK_CTRL2(t0)
	li    t1, 0x8f1
	sw    t1, CLOCK_CTRL2(t0)

	//wait
	li    t2, 0x3
1:
	bnez  t2, 1b
	addiu t2, t2, -1

	li    t1, 0x0f1           // power up pll
	sw    t1, CLOCK_CTRL2(t0)

	//wail lock
	li    t2, 0x40
1:
	bnez  t2, 1b
	addiu t2, t2, -1

	li    t2, 0xbfd00210    //CHIP_SAMPLE0
2:
	lw    t3, 0x0(t2)
	and   t3, t3, 0x00000400  //wait for ready
	nop

	li    t1, 0x10f1		// select pll clk
	sw    t1, CLOCK_CTRL2(t0)
	li    t1, 0x10f0		// clear set bit
	sw    t1, CLOCK_CTRL2(t0)

	//select CPU core frequency here
cpu_pll_cfg:
	//	cpu	[12]sel, [11]pd, [10:8]odf, [7:1]ldf, [0]set
#define CPUPLL_ODF  1
#define CPUPLL_DIV  2
#define CPUPLL_LDF  (CPU_CLOCK_RATE / OSC_CLK * CPUPLL_DIV)

	li a1, (CPUPLL_LDF << CPUPLL_LDF_OFFSET) | (CPUPLL_ODF << CPUPLL_ODF_OFFSET)

	li	t0, CREG_BASE

	or t1, a1, 0x800  //power down
	sw	t1, CLOCK_CTRL0(t0)

	or t1, a1, 0x801  // power down
	sw	t1, CLOCK_CTRL0(t0)

	//wait
	li	t2, 0x100
1:
	bnez  t2, 1b
	addiu t2, t2, -1

	or    t1, a1, 0x001  // power up
	sw    t1, CLOCK_CTRL0(t0)

	//wail
	li    t2, 0x4000
1:
	bnez  t2, 1b
	addiu t2, t2, -1

	li    t2, 0xbfd00210    //CHIP_SAMPLE0
2:
	lw    t3, 0x0(t2)
	and   t3, t3, 0x00000100  //wait for ready
	nop

	or    t1, a1, 0x1001		// select pll clk
	sw    t1, CLOCK_CTRL0(t0)

	or    t1, a1, 0x1000		// clear set bit
	sw    t1, CLOCK_CTRL0(t0)
